`timescale 1ns / 1ps

////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer:
//
// Create Date:   14:20:53 07/30/2015
// Design Name:   ForwardingUnit
// Module Name:   D:/Libraries/Documents/Ingenieria en computacion/Arquitectura Computadoras/TrabajoFinalArquitectura/trunk/Final-Mips/forwardTest.v
// Project Name:  Final-Mips
// Target Device:  
// Tool versions:  
// Description: 
//
// Verilog Test Fixture created by ISE for module: ForwardingUnit
//
// Dependencies:
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
////////////////////////////////////////////////////////////////////////////////

module forwardTest;

	// Inputs
	reg [4:0] Rs;
	reg [4:0] Rt;
	reg [4:0] RdE4;
	reg [4:0] RdE5;
	reg regWriteE4;
	reg regWriteE5;

	// Outputs
	wire [1:0] forwardA;
	wire [1:0] forwardB;

	// Instantiate the Unit Under Test (UUT)
	ForwardingUnit uut (
		.Rs(Rs), 
		.Rt(Rt), 
		.RdE4(RdE4), 
		.RdE5(RdE5), 
		.regWriteE4(regWriteE4), 
		.regWriteE5(regWriteE5), 
		.forwardA(forwardA), 
		.forwardB(forwardB)
	);

	initial begin
		// Initialize Inputs
		Rs = 0;
		Rt = 0;
		RdE4 = 0;
		RdE5 = 0;
		regWriteE4 = 0;
		regWriteE5 = 0;

		// Wait 100 ns for global reset to finish
		#100;
        
		// Add stimulus here 
		// sub $2, $1, 3
		// and $12, 2, 5
		Rs = 2;
		Rt = 5;
		RdE4 = 2;
		regWriteE4 = 1;
		#100;
		//sub $2, $1, $3
		//nop
		//or $13, $2, $6
		regWriteE4 = 0;
		RdE4 = 13;
		Rs = 2;
		Rt = 6;
		RdE5 = 2;
		regWriteE5 = 1;
		#100;
		// sub $2, $1, 3
		// and $12, $5, $2
		Rs = 5;
		Rt = 2;
		RdE4 = 2;
		regWriteE4 = 1;
		#100;
		//sub $2, $1, $3
		//nop
		//or $13, $6, $2
		regWriteE4 = 0;
		RdE4 = 13;
		Rs = 6;
		Rt = 2;
		RdE5 = 2;
		regWriteE5 = 1;
	end
      
endmodule

